2. The Field of the Invention
The present invention comprises a conductor forming process in which ion implantation forms an electrically conductive interconnect within a dielectric layer. The inventive conduct forming process also uses implantation to form a thermally conductive structure that is insulated by and contained within the dielectric layer.
3. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. A substrate assembly refers to a substrate with one or more layers or structures formed thereon. For example, a substrate assembly in the present disclosure can refer to a substrate with interconnects that connect to active areas within the substrate. The interconnects can be within an insulative layer upon the substrate assembly. A semiconductor device can refer to a substrate assembly upon which at least one microelectronic device has been or is being fabricated. The semiconductor device can also refer to a semiconductor substrate assembly having formed thereon elements such as transistors. Interconnection layers are formed on the semiconductor substrate assembly for electrically connecting such elements.
The semiconductor industry has, since the development of the integrated circuit. used a process that required the etching of a hole or via in a dielectric layer and the subsequent filling of the hole with a conductive material to make a connection between one conductive layer and another. The connection was formed of such materials as polysilicon, high melting-point metals, high melting-point metal silicides, aluminum, and aluminum alloys. The ever-increasing pressure to miniaturize and to increase semiconductor device speed has required that both interconnect size and interconnect resistance be reduced. Therefore, semiconductor integrated circuit devices require interconnect structures of smaller lateral dimensions, and require materials that have smaller resistivities. A reliability problem in conventional etched via structures is over etching the via and undercutting a structure with which contact is to be made.
Because hole filling following an etch is problematic, interconnect hole filling seldom achieves a complete connection between the interconnect interface and the electrically conductive region beneath the interconnect. Attempts have been made to create interconnects by forming an interconnect first, followed by forming a dielectric layer, for example, by filling the regions between interconnects with a gelatinous material and curing the material into a solid dielectric. Thus, hole filling is avoided, however, there remains a discrete interface between the interconnect and the electrically conductive region that the interconnect contacts.
Additionally, as semiconductor device dimensions continue to shrink in size the problem of heat management continues to increase in complexity. As heat management requirements continue to increase, methods of removing heat from the semiconductor device without increasing the vertical or lateral geometries of the devices are constantly being sought.
What is needed is a method of forming an interconnect without the prior art via etching and via hole-filling process. What is also needed is a method of forming an interconnect wherein the interconnect minimizes interface discontinuities between the electrically-conductive region beneath the interconnect and the interconnect itself. What is also needed is a method of forming an interconnect that resists thermal cycle stresses at the interface with the dielectric material and with the electrically conductive region beneath the interconnect. What is also needed is a method of forming heat management structures within semiconductor devices without increasing the vertical or lateral geometries of the devices.
The present invention is directed toward the formation of an interconnect that is not within an etched via. Interconnect formation is accomplished through ion implantation into several levels within a dielectric layer. Ion implantation penetrates into an electrically conductive region beneath the dielectric layer and continues in discreet, overlapping implantations up to the top of the dielectric layer, thus forming a continuous interconnect.
Structural qualities achieved by the method of the present invention include a low resistivity between the interconnect and the conductive region. There is also a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted, and between the interconnect and the electrically conductive region beneath the interconnect.
Implantation elements may be selected in connection with dielectric materials so that heat treatment will cause continuous metallic structures to form within the interconnect implantation area by dissociation of metallic elements from the dielectric material and the combination of these dissociated elements with the implanted metal ions.
The present invention is also directed toward the implantation of ion dosages and depths that are selected so as to form heat-management structures that are entirely insulated within the dielectric layer. Heat-management structures of the present invention have coefficients of thermal conductivity that are greater than the coefficients of thermal conductivity of the preferred dielectric materials. Implantation can also simultaneously form semiconductor active areas with interconnect formation by the implantation methods of the present invention.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.